A turbo-PLONK program P can be thought of as sequence of states v∈Fw, where the state size w is chosen by the program designer. The proof size and prover run time increase linearly in w and standard choices are 3 or 4.
A valid execution trace T∈(Fw)t for Psatisfies P's transition gate and copy constraint.
transition gate - A transition constraint of P is a 2w+ℓ -variate degree at most d polynomial P , where d is the degree of P, and is recommended to be set to w+1, and ℓ is the selector number.
The transition gate of P consists of all the transition constraints together with ℓ selector vectors q1,…,qℓ∈Ft. T is said to satisfy the transition gate if for each transition constrainti∈[t] , P(Ti,1,…,Ti,w,Ti+1,1,…,Ti+1,w,q1(i),…,qℓ(i))=0.
copy constraint - this is a partition of w×t into distinct sets {Si} . T is said to satisfy the copy constraint if Ti,j=Ti′,j′ whenever (i,j) and (i′,j′) belong to the same set in the partition.
Let's see how an arithmetic circuit can be represented in this format. Every row will correspond to a gate, and the row values will be the incoming and outgoing wire values of the gate; so to represent fan-in t circuits we'll use w=t+1. For example, for fan-in 2 the row values v1,v2,v3 will correspond to the left,right and output wire values of the gate associated with the row.
The transition constraints will be somewhat "degenerate" in the sense that we won't use the "next row" valuesTi+1,1,…Ti+1,w. They will check if the correct input and output relations hold inside the row according to whether it's an addition or multiplication gate. This can be done with 3 selectors and one constraint polynomial P of degree t+1 . E.g., for fan-in 2 we use:
P(qL,qR,qM,x1,x2,x3):=qL⋅x1+qR⋅x2+qM⋅x1x2−x3
By setting qL(i)=qR(i)=1,qM(i)=0 for an addition gate and qL(i)=qR(i)=0,qM(i)=1 for a multiplication gate, we can see the above equation checks the correct input/output relation in both cases.
The copy constraint will enforce the wiring of the circuit. For example, if the left wire of the 4th gate is the output wire of the second gate, we will enforce T2,3=T4,1.